VLSI CAD Part I: Logic

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VLSI CAD Part I: Logic

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Beschreibung

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About this course: A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc. How do we design these complex chips? Answer: CAD software tools. Learn how to build thesA modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the maj…

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When you enroll for courses through Coursera you get to choose for a paid plan or for a free plan

  • Free plan: No certicification and/or audit only. You will have access to all course materials except graded items.
  • Paid plan: Commit to earning a Certificate—it's a trusted, shareable way to showcase your new skills.

About this course: A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc. How do we design these complex chips? Answer: CAD software tools. Learn how to build thesA modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this first part of the course is on key Boolean logic representations that make it possible to synthesize, and to verify, the gate-level logic in these designs. This is the first step of the design chain, as we move from logic to layout. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: Computational Boolean algebra, logic verification, and logic synthesis (2-level and multi-level). Recommended Background Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Exposure to basic VLSI at an undergraduate level is nice -- but it’s not necessary. We will keep the course self-contained, but students with some VLSI will be able to skip some background material.e tools in this class.

Who is this class for: You should be taking this course if (1) you are interested in building VLSI design tools; (2) you are interested in designing VLSI chips, and you want to know why the tools do what they do; (3) you just like cool algorithms, that work on big cool problems that involve bits, and gates, and geometry, and graphs, and matrices, and time, etc.

Created by:  University of Illinois at Urbana-Champaign
  • Taught by:  Rob A. Rutenbar, Adjunct Professor

    Department of Computer Science
Level Intermediate Language English How To Pass Pass all graded assignments to complete the course. User Ratings 4.7 stars Average User Rating 4.7See what learners said Coursework

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Syllabus


WEEK 1


Orientation
In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course.


1 video, 2 readings, 1 practice quiz expand


  1. Video: Welcome and Introduction
  2. Reading: Syllabus
  3. Practice Quiz: Demographics Survey
  4. Reading: Tools For This Course
  5. Ungraded Programming: KBDD
  6. Ungraded Programming: MiniSat
  7. Ungraded Programming: Espresso
  8. Ungraded Programming: SIS


Computational Boolean Algebra
In this module, we will introduce advanced Boolean algebra math concepts that make it possible to take a "computational" approach to Boolean algebra.


6 videos, 2 readings expand


  1. Reading: Week 1 Overview
  2. Video: Computational Boolean Algebra: Basics
  3. Video: Computational Boolean Algebra: Boolean Difference
  4. Video: Computational Boolean Algebra: Quantification Operators
  5. Video: Computational Boolean Algebra: Application to Logic Network Repair
  6. Video: Computational Boolean Algebra: Recursive Tautology
  7. Video: Computational Boolean Algebra: Recursive Tautology—URP Implementation
  8. Reading: Week 1 Assignments


WEEK 2


Boolean Representation via BDDs and SAT
Week 2 introduces two powerful and important representation techniques that allow us to do SERIOUS computational Boolean algebra, on industrial-scale designs.


7 videos, 2 readings expand


  1. Reading: Week 2 Overview
  2. Video: BDD Basics, Part 1
  3. Video: BDD Basics, Part 2
  4. Video: BDD Sharing
  5. Video: BDD Ordering
  6. Video: Satisfiability (SAT), Part 1
  7. Video: Boolean Constraint Propagation (BCP) for SAT
  8. Video: Using SAT for Logic
  9. Reading: Week 2 Assignments

Graded: Problem Set #1
Graded: Programming Assignment #1: Unate Recursive Complement

WEEK 3


2-Level Logic Synthesis, and Multi-Level Logic Synthesis via the Algebraic Model
In Week 3, we will move from "representing" things to "synthesizing" things. In this case, synthesis means "optimization", or maybe the word "minimization" is more familiar from hand work with Kmaps or Boolean algebra.


8 videos, 2 readings expand


  1. Reading: Week 3 Overview
  2. Video: 2-Level Logic: Basics
  3. Video: 2-Level Logic: The Reduce-Expand-Irredundant Optimization Loop
  4. Video: 2-Level Logic: Details for One Step: Expand
  5. Video: Multilevel Logic and the Boolean Network Model
  6. Video: Multilevel Logic: Algebraic Model for Factoring
  7. Video: Multilevel Logic: Algebraic Division
  8. Video: Multilevel Logic: Role of Kernels and Co-Kernels in Factoring
  9. Video: Multilevel Logic: Finding the Kernels
  10. Reading: Week 3 Assignments

Graded: Problem Set #2

WEEK 4


Multilevel Factor Extract and Don't Cares



You now know that to factor a multi-level network to reduce its complexity, you must look at the kernels and co-kernels. You know how to "get" these for any node. But -- what do you do with a big network to actually FIND the right common divisors? This is called EXTRACTION. We then look at a new opportunity to optimize multi-level logic: Don't Cares. In simple designs, we usually regard Don't Cares as "impossible inputs" -- things that just do not happen, so we can choose the value the hardware creates to minimize the logic.


8 videos, 2 readings expand


  1. Reading: Week 4 Overview
  2. Video: Mulitlevel Logic and Divisor Extraction—Single Cube Case
  3. Video: Mulitlevel Logic and Divisor Extraction—Multiple Cube Case
  4. Video: Multilevel Logic and Divisor Extraction—Finding Prime Rectangles & Summary
  5. Video: Multilevel Logic—Implicit Don't Cares, Part 1
  6. Video: Multilevel Logic—Implicit Don't Cares, Part 2
  7. Video: Multilevel Logic—Satisfiability Don't Cares
  8. Video: Multilevel Logic—Controllability Don't Cares
  9. Video: Multilevel Logic—Observability Don't Cares
  10. Reading: Week 4 Assignments

Graded: Problem Set #3
Graded: Programming Assignment #2: Serious BDDs
Graded: Auxiliary Quiz of Serious BDDs

WEEK 5


Final Exam
There is no new content this week. Instead, you should focus on finishing the last problem set and completing the Final Exam.


1 practice quiz expand


  1. Practice Quiz: End of Course Survey

Graded: Problem Set #4
Graded: Final Exam

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